The present invention relates to semiconductor devices and more specifically to a field effect transistor (“FET”) in which a stress is applied to a channel region of the FET.
Increasingly, stressor elements are being incorporated into FET semiconductor devices and/or ancillary structures overlying such devices in order to increase the performance of the FETs. It is known that a compressive stress applied to the channel region of a p-type conductivity FET or “PFET” creates a compressive strain within the semiconductor crystal lattice structure of the channel region which increases the performance of the PFET. On the other hand, a tensile stress applied to the channel region of an n-type conductivity FET or “NFET” creates a tensile strain within the semiconductor crystal lattice structure of the channel region which increases the performance of the NFET. In each case, the stress applied to the channel region creates a strain therein which improves the mobility of charge carriers to improve the transistor's performance.
Typically, FETs within integrated circuits are fabricated as symmetric devices. The drain and the source of the transistor are subjected to the same processing steps. For example, when an ion implantation is made to a side of the FET at which the drain is disposed (the “drain side”), the ion implantation is also made to the side of the FET at which the source is disposed (the “source side”). Thus, when an ion implantation is made at an angle to a drain side of the FET, the ion implantation is mirrored and performed to the source side of the FET as well, to provide a symmetric FET device structure. This permits the FET to be incorporated and utilized in a layout of the integrated circuit without limiting one side of the FET to functioning as only the drain side and limiting the other side of the FET to functioning only as the source side.
Accordingly, in FET structures which incorporate stressor elements, such stressor elements apply stresses to the channel region in essentially equal magnitudes from both a source side and from a drain side of the FET. However, several undesirable side effects are associated with these stresses, which are only now being recognized. One such side effect is reduced bandgap, which manifests itself as a lowering of the threshold voltage. When the bandgap and threshold reduction takes place on the drain side of the FET, this aggravates the effect referred to as drain-induced barrier lowering (“DIBL”). Reduced drain-side bandgap increases the sensitivity of the FET to drain voltage. As a result, when the magnitude of the voltage applied to the drain of the FET increases, the magnitude of the threshold voltage becomes smaller. Consequently, the threshold voltage (“Vt”) is different depending on whether the magnitude of the drain to source voltage (|Vds|) has a high value or has a low value.
This effect is illustrated in FIG. 2. Curve 210 depicts the change in the magnitude of the threshold voltage (|Vt|) in relation to the magnitude of the drain to source voltage |Vds| for an FET to which no more than a low level of stress is applied to the channel region of the FET. Curve 220 depicts the change in the magnitude of the threshold voltage (|Vt|) in relation to the magnitude of the drain to source voltage |Vds| for an FET to which a high level of stress is applied to the channel region of the FET. For an FET, these values of Vt and Vds are both positive. When Vds is low, Vt is referred to as a “linear Vt” or “baseline Vt” (“Vtlin”). When Vds is at a positive high value for an NFET, the NFET is driven into saturation. At such value, the threshold voltage is referred to as a “saturation Vt” or “Vtsat”. As depicted in curves 210 and 220 of FIG. 2, the threshold voltage for both the low-stress FET and the high-stress FET decrease in relation to the magnitude of Vds. In this example, both curves start from one level 212, 222 where Vtlin for the low-stress FET and Vtlin for the high-stress FET are the same. Then, with increasing Vds, the curves decrease to a level at which the value of Vtsat (224) for the high-stress FET is lower than Vtlin (222) and the value of Vtsat (214) for the low-stress FET is lower than its Vtlin (212). The undesirable DIBL side effect can be quantified as a difference between these two threshold voltage values, i.e., expressed as the formula:Vtsat minus Vtlin.
As can also be seen from FIG. 2, one effect of applying stress to the channel region of the FET from both a source side and a drain side of the FET is that the value of Vtsat (214) reached for the high-stress FET is lower than the value of Vtsat (214) reached for the low-stress FET. This effect represents an increased impact of DIBL upon the high-stress FET, and thus, increased performance degradation for the high-stress FET.
One impact is seen in a relative reduction in performance that results from process steps employed to correct for this effect. FETs are designed to operate with a threshold voltage having a targeted value. FETs are also designed to conduct a targeted amount of current or “on-current” when the FET is fully turned on. In FETs which incorporate stressor elements such as described above, the reduction in the threshold voltage brought about by DIBL must be compensated in order for the transistor to operate with the targeted threshold voltage value. Such compensation can be made by increasing the dopant concentrations of halo regions and/or well regions of the transistor. Unfortunately, increased dopant concentrations in such regions are known to decrease the mobility of charge carriers within the transistor. In view of the foregoing, this leads to paradoxical results in that corrective changes to the FET that are required to compensate for unwanted side effects of the applied stresses cause a decrease in performance which sometimes partially or even completely negates the improvement in mobility brought about by the applied stresses.
In addition to that described in the foregoing, another side effect of the applied stresses is an increase in the output conductance of the FET, as best seen in FIG. 3. FIG. 3 is a logarithmic plot of the drain current (“Id”) of an FET in relation to the drain-source voltage (“Vds”) applied to the FET. Curve 310 illustrates a case in which no deliberate effort has been made to impart a stress to the channel region of the FET. Curve 320 illustrates a case in which a stress is imparted to the channel region via stressor elements as described above. Upon comparison of the curves, it is seen that curve 320 exhibits higher output conductance, in that the slope of the curve 320 in the conductive region of operation (at higher levels of Vds) is greater than the slope of the curve 310 for the FET for the transistor which does not have the stresses applied thereto. Lower output conductance, as exemplified by curve 310, which has a flatter characteristic at higher values of Vds is desirable for FETs used in current mirror circuits and for transistors used to provide analog amplification.
Lower output conductance is also desirable for transistors used in PLLs (phase-lock-loops) and those used in output drivers within digital integrated circuits such as microprocessors.
Another undesirable side effect is reduced control of the threshold voltage of the FET. This occurs because the strain produced within the FET channel region by the applied stresses affects the threshold voltage. Moreover, since the magnitude of the strain produced within the channel region is subject to vary due to variations in processing, the achieved threshold voltage is subject to greater variability.
Furthermore, another unwanted side effect that may occur is greater device degradation of the FET due to a mechanism such as negative bias temperature instability or “NBTI”.
It should be noted with respect to the foregoing that stresses applied to the channel region of the FET principally increase the low-field mobility. However, this improvement is made without significantly improving the value of carrier saturation velocity “vsat” within the FET. The positive effects of the applied stresses are limited to the source side of the FET. In addition, as discussed above, the negative side effects are limited to the drain side of the FET.